For many computer systems, memory latency is a significant obstacle when accessing a memory address. Over 90% of the time required of a computer system to execute a particular algorithmic function may be spent waiting to receive a response to a read request because of memory latency. When the computer system's algorithm accesses memory, the system dispatches the read request to the memory, waits for the memory port to return the requested data, and then the algorithm applies the returned data. An algorithm may frequently request data from a subsequent memory address based on the returned data. Applying the returned data and issuing a subsequent memory read request can take little time compared to the time spent waiting for the memory port to return the requested data. Therefore, reducing memory latency can improve system performance in systems that rely heavily on memory access, such as the system described above. When multiple instances of the algorithm operate independently in parallel without any interactions, several read requests to the memory ports may be pending at any given time. The latency one algorithm experiences is then dependent upon the read request frequency of the other units performing the same algorithm because access to a memory port is serial.